First, an image sensing device described in Japanese Patent Laid-Open No. 2000-253280 will be described below as prior art. In this reference, explanation is made by using a digital still camera shown in FIG. 2 as an embodiment. In this digital still camera, an image of a desired object is sensed by a solid-state image sensor, and an image signal representing the image is converted into digital image data and recorded in a recording medium such as a memory card. The recorded image data can be read out at any arbitrary time, and the image represented by this image data can be loaded into a personal computer or the like and subjected to predetermined processing.
Some known digital still cameras of this type include a display device such as a liquid crystal monitor. In this case, as shown in FIG. 3 of the same reference, a driving signal (FIG. 3(a) of the reference) for reading out an image at a predetermined frame rate, e.g., 15 to 30 frames/sec (to be referred to as fps hereinafter) is supplied from a system controller 130 shown in FIG. 2 of the reference to an image sensor 104 shown in FIG. 2 of the reference. Accordingly, an image signal from the image sensor 104 shown in FIG. 2 of the reference is converted into digital image data by an A/D converter 106 shown in FIG. 2 of the reference. This digital image data is subjected to predetermined processing by a signal processing circuit 108 shown in FIG. 2 of the reference, and sequentially loaded into a buffer memory 114 shown in FIG. 2 of the reference via a memory controller 112 shown in FIG. 2 of the reference (FIG. 3(b) of the reference).
Then, the memory controller 112 shown in FIG. 2 of the reference sequentially reads out the image data loaded into the buffer memory 114 shown in FIG. 2 of the reference, and supplies the readout data to a video playback circuit 112 shown in FIG. 2 of the reference. Consequently, images supplied field by field from the video playback circuit 112 shown in FIG. 2 of the reference are sequentially displayed on a liquid crystal monitor 124 shown in FIG. 2 of the reference (FIG. 3(c) of the reference).
A user frames an image of an object by using this digital viewfinder function. To set photographing conditions, e.g., exposure compensation and a shutter speed, the user turns on a menu display switch of operation switches 126 shown in FIG. 2 of the reference to display an operation menu on the liquid crystal monitor 124 shown in FIG. 2 of the reference, and inputs the photographing conditions.
While this operation menu is displayed, the image sensing device described in the reference delays the driving signal to the image sensor (FIG. 4(a) of the reference) or intermittently loads image frames from the image sensor (FIG. 5(b) of the reference). In this manner, the image sensing device reduces the number of image frames to be loaded from the image sensor and lowers the frame rate of an image to be displayed, thereby reducing the battery consumption and improving the ease with which display characters are seen.
As another prior art, an image data processing apparatus described in Japanese Patent Laid-Open No. 8-149435 will be explained below. An embodiment of this reference is a television telephone system shown in FIG. 1 of the reference. The network transmission capability of this system is not sufficiently high. Therefore, as shown in FIG. 1 of the same reference, a signal of a video camera VC is converted into a digital signal by an A/D converter ADC. After that, this digital signal is subjected to a compression/filtering process by an image data compressor VDCP and transferred across a network via a line driver LD.
In the image data compression/filtering process, an image signal is processed frame by frame, and an image to be processed is divided into blocks each having a predetermined number of pixels having a horizontal or vertical spread. Therefore, this process requires a relatively long time before the processing result is determined. Accordingly, the system has image memories (buffer memories described in Japanese Patent Laid-Open No. 2000-253280) VRAM1 and VRAM2 (FIG. 2 of the reference) each capable of storing one image frame subjected to image processing such as compression and filtering. When one of these image memories receives an image frame which is output after being processed, the other image memory outputs an immediately preceding processed image frame, and the two memories alternately repeat these input and output operations (FIG. 3 of the reference).
Image data transmitted across the network is subjected to a receiving process which is the reverse of transmission, i.e., decoded and D/A-converted via a line receiver LR and displayed on a television monitor TV. A synchronous signal of an image data processor VDP is extracted by and output from an image controller VCTRL. Similar to the image data compressor VDCP, an image data decoder VDRS is constructed by using two image memories. These two image memories VRAM1 and VRAM2 may also be implemented by one dual-port image memory DPVRAM (FIG. 4 of the reference) capable of storing two processed image frames.
This television telephone system realizes image processing which is apparently performed frame by frame in real time, and thereby displays motion images on a television monitor, with an inexpensive arrangement having only an image memory area for two processed image frames.
Unfortunately, the above prior art references have the following problems. For example, to clearly photograph the motion of a rapidly moving object such as in sports, a motion image is recorded at the frame rate of image sensing. Therefore, this image sensing frame rate must be increased.
When the image sensing frame rate is made higher than the display rate, the following problem arises if the buffer memories are controlled by the means of the prior art described in Japanese Patent Laid-Open No. 2000-253280. That is, in this reference, sensed image frames are sequentially displayed. Therefore, if the image sensing frame rate is lower than the display rate, image frames can be displayed at the image sensing frame rate. However, if the image sensing frame rate becomes higher than the display rate, no image frames can be expressed. In this case, therefore, even though the frame interval of image sensing is smaller than the interval of display update, display is updated once for one sensed image frame, resulting in a digital viewfinder slower than an actual motion. Furthermore, the buffer memories are finite, and sensed image frames can be buffered more faster than when they are displayed. Consequently, an image frame is overwritten while it is displayed, or an image frame which cannot be displayed is generated.
Also, when the image sensing frame rate is made higher than the display rate, the following problem arises if the image memories are controlled by the means of the prior art described in Japanese Patent Laid-Open No. 8-149435. That is, in this reference, the input and output image memories are switched for each frame. Accordingly, information in the image memories breaks if inputting and outputting are not synchronized.